In portable battery operated radio transceivers it is always desirable to use the available battery power efficiently in order to prolong the use of the battery and thus reduce the significant expense and frequency of battery replacement or recharging. It is also clearly desirable to minimize circuit complexity as well as maintenance requirements while simultaneously consistently obtaining good performance with a reduction in cost and size.
As to the inclusion of power conservation features, such considerations are particularly important in transceivers employing a frequency synthesizer since such circuits are typically responsible for a significant portion of the overall power consumption. For example, in systems without power conservation features, the receiver section of the transceiver is conventionally operated in a "standby" mode when no received signal of significant strength is present. The transmitter section would also operate in the "standby" mode in the absence of the toggling of a push-to-talk switch. However, since transceiver components may remain active for substantial periods of time in the relatively high power consumption standby mode while awaiting the occurrence of incoming signals or activation of the transmitter, such standby modes can nevertheless result in significant waste of battery power.
For these reasons various attempts in the prior art have been made so as to provide for conservation of power in the standby mode. For example, one solution known in the prior art is to repeatedly turn the entire receiver section on and off while operating in the standby mode in such a manner that the "on" time or duty cycle is substantially shorter in duration than the "off" intervals. Examples of such systems are found in U.S. Pat. Nos. 4,419,765 to Wycoff et al, 4,531,237 to Bar-on et al and U.S. Pat. No. 4,736,461 to Kawasaki et al.
Another example may be found in U.S. Pat. No. 4,521,918 issued to Challen on Jun. 4, 1985 which discloses a battery saving frequency synthesizer arrangement wherein power to the phase-lock loop section of the synthesizer is periodically turned off. However, a control signal is provided during the power interruption for the purpose of maintaining the voltage controlled oscillator (VCO) frequency in order to prevent frequency drift. This feature allows the phase-lock loop to lock into a stable frequency in a short time period.
Under such power conservation circumstances for standby modes in radio transceivers, power to the circuits associated with the transmitter is also turned off to conserve battery power. Among such circuits is the transmitter voltage controlled oscillator in the frequency synthesizer. Such oscillators are conventionally locked to a very stable and accurate crystal-controlled oscillator in a feedback loop which compares a fraction of the desired output frequency with a reference frequency provided by the crystal-controlled oscillator, and a difference in the noted frequencies is used to generate a change in the voltage controlling the VCO in order to reduce the difference to zero.
However, a problem is produced under such circumstances since in certain applications it is necessary when switching between receive and transmit modes of operation that the VCO reaches it stable output frequency in the shortest time possible. When the oscillator is allowed to run continuously, it is relatively easy to quickly obtain a stable desired output frequency. The desired result, however, is not easily obtained when the oscillator is not operating continuously, since when power is first applied to the VCO, there is a much greater rate of change of frequency in the first few milliseconds than in later time intervals. Moreover, where this rate of change is greater than the ability of the control voltage to track it, the output frequency will not be stable or quickly settle to the desired frequency.